System Verilog

Design and Verification of DDR SDRAM Memory Controller Using SystemVerilog For Higher Coverage

P. Kumar M.P. and S. K. Panda, 'Design and Verification of DDR SDRAM Memory Controller Using SystemVerilog For Higher Coverage,' 2019 International Conference on Intelligent Computing and Control Systems (ICCS), Madurai, India, 2019, pp. 689-694, doi: 10.1109/ICCS45141.2019.9065407.